The present invention relates to a method of making semiconductor integrated circuit device and, more particularly, to a method of making a bipolar LSI (Large Scale Integrated Circuit).
As a measure for electrically isolating the semiconductor elements (transistors) of a semiconductor integrated circuit device (referred to as IC device, hereinafter), an isolation method making use of semiconductive oxides is becoming popular. This method is superior to the conventional PN junction and isolation method in that the occupied area is made small, so as to contribute to further improve the scale of integration of the IC device.
The current demand of increment of number of circuit facilities in one IC device requires a further increased scale of integration of transistors.
The isolation by means of the oxide film is effective in diminishing the occupied area as compared with the PN junction, as stated above, but inconveniently requires an uneconomically large isolation region, which well reaches about 70% of the chip area, due to the lateral spreading of the isolating semiconductor oxide layer. This goes quite contrary to the demand for the increment of the scale of integration.
More specifically, the isolation by means of the oxide film is effected by heating and oxidizing a part of the semiconductive substrate. During this heating, the oxide unfavourably forms bird-heads 27 and bird-beaks 26 as shown in FIG. 1, due to the thermal expansion of the same, so as to hinder the increment of the integration scale. In this FIG. 1, 1 is a P type silicon wafer, 2 is a N.sup.+ type buried layer and 8 is an N type layer.
In forming LSI, especially the bipolar LSI, an N.sup.+ type buried layer is usually formed in each transistor, in order to minimize the serial resistance of collectors. This N.sup.+ type buried layer formed on the P type silicon substrate inconveniently spreads laterally, so that it is necessary to space adjacent N.sup.+ type buried layers away from each other by a sufficiently large distance, in order to obtain the characteristics necessary for the isolation. In addition, it is necessary to preserve a masking margin between the N.sup.+ type buried layer and the isolating oxide layer. For these reasons, the improvement of the integration scale has been hindered also by the N.sup.+ type buried layer.
Further, in forming transistors in a semiconductive substrate surrounded by the semiconductor oxide layers, photo etching process is indispensable for forming the emitter regions, base regions and high concentration diffusion region for leading out the collector electrodes, and for perforation in the oxide for forming the wiring contact for these regions.
In carrying out this photo etching process, it is a common measure to preserve a sufficiently large masking margin, making use of the fact that the oxide layer of the isolation region has a thickness greater than that of the oxide layer on the portion of the semiconductive substrate where the transistor is formed. Consequently, the oxide on the isolation region is partially etched to cause a more drastic difference of the height between the oxides.
More specifically, according to the prior art technic, the transistor has been formed through perforating the oxide film 28 on the substrate, in contact with the isolating semiconductor oxide 25, as will be seen FIG. 2. However, since the etching rates or speeds of the oxide film 28 on the substrate and the isolating semiconductor oxide 25 are equal, both of them are etched in the course of the photo etching for the perforation. Consequently, the junction areas, where the semiconductor oxide film is contacted by the emitter 21, base 7 and collector 16, are inconveniently grooved as at 29, resulting in various inconvenience such as shortcircuitting across the junction, breakage of the wiring and pin holes or cracks in the intermediate insulation layer in the multi-layered wiring construction.
Various proposals and attempts have been made to overcome these problems. One of these attempts is to form a diffusion layer 30 of high concentration at the side wall portion of the semiconductor oxide film, so as to make the depth of the base layer at above mentioned junction area larger. Another method is to carry out the high-concentration diffusion for forming the base, so that the oxide film may not be formed to have a large thickness at the time of the diffusion, and to take a step of washing out before the Al evaporation.
These countermeasures are, however, disadvantageous in that they cause an increase of parasitic capacitance of the junction and larger depth of the base, resulting in a narrower current-gain range of the transistor, which makes it extremely difficult to obtain a high speed semiconductor integrated circuit device.
The specifications of U.S. Pat. Nos. 3,659,160; 3,775,001; 3,997,378 and 4,042,726 disclose a method for making a semiconductor integrated circuit device having steps of forming an active region of a desired depth in the semiconductive substrate, by means of diffusion, forming a plurality of grooves in the semiconductive substrate by a selective etching, in order to divide the active diffusion region into a plurality of sections, and then forming oxide films in the grooves. According to this method, an impractically long etching time is required, since the semiconductive substrate has to be etched deep enough to divide the active diffusion region. In addition, this etching process inconveniently causes an etching of the substrate in the lateral direction, i.e. the side etching, resulting in a larger width of each groove. Consequently, the area occupied by the isolation region is rendered undesirably large.